This invention relates to a data integrity checking apparatus for use, for example, in repeatedly checking the integrity of data, such as program instructions, held in a block of RAM.
Various checking arrangements have already been proposed in which successive words of the stored data are supplied to the checking apparatus and a checksum value is generated. This is checked against a known result to determine whether the data is correct. However, there is a danger with apparatus of this type that, as a result of a failure of a component of the checker, the output thereof could remain xe2x80x9cstuckxe2x80x9d at a previously determined correct value.
It is an object of the present invention to provide a data integrity data checking apparatus in which this difficulty is avoided.
A data integrity checking apparatus in accordance with the invention comprises an array of n latch circuits, an array of n exclusive OR gates having output terminals connected to the input terminals of respective ones of the latch circuits, the exclusive OR gates receiving as one input, bit-rotated words from the outputs of the latch circuits and as another input successive words of the data to be checked.
The number of bits by which words are rotated in each cycle is an even number when n is odd and an odd number when n is even, so that each bit of the checksum is passed through every latch and exclusive OR gate.
Preferably, when the word length n is 32, the bit-rotated words from the outputs of the latch circuits are bit-rotated by 3 bits.
The apparatus preferably includes means for serially clocking out the final word held by the latch circuits from one of the latch circuits.
In accordance with another aspect of the invention there is provided a digital processing system including a program instruction RAM store and a an apparatus for checking the integrity of the data stored in said program instruction RAM store, said apparatus comprising an array of n latch circuits, an array of n exclusive OR gates with outputs connected to the inputs of respective ones of the latch circuits, the outputs of the latch circuits being connected to the inputs of the exclusive OR gates so as to apply thereto a bit-rotated word, and an address controller connected to the RAM store so as to cause it to output the data stored therein in successive n-bit words to the exclusive OR gate array in synchronism with clocking of data from the exclusive OR gate array into the latch circuit array.
Preferably, the RAM store data is arranged so that the n words at the highest addresses thereof are set to zero, so that an output word can be serially clocked out of one of the latch circuit during the last n clock events of each test cycle.